This invention relates to an integrated circuit semiconductor memory device such as an SRAM (Static Random Access Memory) or latch that provides increased node capacitance for protection against soft errors.
Semiconductor memory devices such as RAM (random access memory) generally include a number of memory cells each formed of a number of transistors. Generally, two storage transistors are coupled between two pass gate transistors, and a bit line is coupled to each of the pass gate transistors. Each pass gate transistor has a gate electrode coupled to a word line, and an address signal is provided on the word line associated with a particular memory cell in order to select that memory cell and read out the stored data therefrom. With the memory cell so selected, its data is read out from the memory node of the memory cell (or data is written therein) through the pass gate transistors via the bit lines. It is of course important that the data stored in the memory cell remain unchanged until it is read out.
There has been a growing difficulty in preserving such stored data as the scale of integration grows higher and higher and the physical size of the memory cell elements decreases. This difficulty arises from what are known as soft errors, which are caused primarily by an alpha particle striking one of the memory nodes, or may be caused by circuit noise. This can cause the voltage on the memory nodes to change, sometimes sufficiently so that a logic 1 is transformed into a logic 0 or vice versa. The amount of voltage change for a given alpha particle hit is inversely proportional to the capacitance on the memory node, and so a relatively large capacitance on the memory node reduced the amount of voltage change for a given alpha particle hit and correspondingly reduces the chance of a soft error.
With the relatively large devices of smaller scale integration, there was sufficient node capacitance to prevent soft errors most of the time. However, as the dimensions of the memory cells are scaled down to fit more devices on the chip, the node capacitances are getting correspondingly very low. In addition, the applied voltage Vdd is also being scaled down with device size, again leading to reduced node capacitance. The result is a high susceptibility to circuit noise and radiation, which in turn leads to an unacceptably high soft error rate.
It would therefore be highly desirable to increase the node capacitances of SRAMs, latches and the like without resorting to increasing the device size again.